A Fully Integrated Low Dropout Regulator

Aim: the main aim of this project is to design "a low- voltage low-dropout regulator "
Abstract:
A low-voltage low-dropout (ldo) regulator that converts an input of 1 v to an output of 0.85–0.5 v, with 90-nmcmos technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (ea), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the ldo regulator. In the rail-to-rail output stage of the ea, a power noise cancellation mechanism is formed, minimizing the size of the power mos transistor. Furthermore, a fast responding transient accelerator is designed through the reuse of parts of the ea. These advantages allow the proposed ldo regulator to operate over a wide range of operating conditions while achieving 99.94% current efficiency, a 28-mv output variation for a 0–100 ma load transient, and a power supply rejection of roughly 50 db over0–100 khz. The area of the proposed ldo regulator is only0.0041 mm2, because of the compact architecture.
Existing system:
Fig:the single-transistor-control ldo based on the fvf topology. Fig: the fvf based ldo with inserted buffer.
Proposed system:
Fig: proposed ldo circuit
Tools: h – spice tool, micro wind, digital schematic.
References:
[1] m. Jeong et al., "a 65 nm cmos low-power small-size multistandard, multiband mobile broadcasting receiver soc, " in ieee int. Solid-state circuits conf. Dig. Tech. Papers (isscc), feb. 2010, pp. 460–461.