Carbon Nanotubes Blowing New Life into NP Dynamic CMOS

Aim:
The main aim of the project is to design "carbon nano tubes blowing new life into np dynamic cmos circuits"
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(abstract)
Low-power, compact, and high-performance np dynamic cmos circuits are presented in this paper assuming a 16 nm carbon nano tube transistor technology. The performances of two-stage pipeline 32-bit carry look ahead adders are evaluated based on hspice simulation with the following four different implementations: silicon mosfet (si-mosfet) domino logic, si-mosfet np dynamic cmos, carbon nano tube mosfet (cn-mosfet) domino logic, and cn-mosfet np dynamic cmos. While providing similar propagation delay, the total area of cn-mosfet np dynamic cmos adder is reduced
Proposed architecture:
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Advantage:
Ø the well-known area and power consumption disadvantages of the np dynamic cmos circuits are eliminated by employing a carbon nanotube transistor technology.
Ø the cn-mosfet np dynamic cmos circuit effectively suppresses both dynamic switching and leakage power consumption while providing similar propagation delay and miniaturizing the area as compared to both silicon and carbon nanotube domino logic circuits.
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Block diagram:
Top-view of a cn-mosfet. Static cmos inverter with cn-mosfets
A multi-stage np dynamic cmos pipeline with carbon nanotube transistors
Tools: hspice_va-2008.03, t-spice
Reference:
[1] v. Kursun and e. G. Friedman, multi-voltagecmos circuit design. New york, ny, usa: wiley, 2006.
[2] s. B.Wijeratne, n. Siddaiah, s. K.Mathew, m. A. Anders, r. K. Krishnamurthy,
J. Anderson, m. Ernest, and m. Nadine, "a 9-ghz 65-nm intel pentium processor integer execution unit, " ieee j. Solid-state circuits, vol. 42, no. 1, pp. 26–37, jan. 2007.