Verific'S Parser Platform

Electra's management team is composed of individuals with experience in Electronic design Automation and business solutions. The core team has extensive experience in managing and developing software solutions in a wide range of technology.
Partners:

Abhijit Chakrabarty - President
With more than 10 years of experience in project management and software development, Abhijit's core expertise is in algorithm development and software design. His unique expertise is in synthesis tools for Verilog and VHDL coupled with in-depth knowledge and understanding of Object-oriented programming with C++. Years of technical management made him ideal in the team. Prior to joining Electra, he was with Delsoft India Pvt Ltd. in Calcutta, as a manager for their synthesis product 'Concorde'. The product was successfully delivered to industry leaders like Synopsys, Fujitsu and Intel. Before that, he was with Exemplar logic, USA, now a part of Mentor Graphics. He picked up the responsibility for both Verilog, Vhdl language synthesis and became a manager of the group. He was also involved with the development of a FPGA partitioning product, for dividing a big circuit into multiple FPGAs and creating the connectivity at the board level. He also developed a interface to IBM synthesis tool 'HIS' and Verilog language. He holds a BS in Electronics and Electrical Communications from Indian Institute of Technology, Kharagpur.